The Kwurdi debug core is written in 100% ARM assembly. It's a very easy and very powerful instruction set. For example, almost all instructions can be conditionally executed, and almost as many will only update the CPU status flags (Zero flag, carry flag, overflow flag, etc.) optionally. Really great features for optimization.
Example:
Code:
tst r0, #1 @ Test bit-0 in r0 and update CPU flags
orrnes r0, r0, r1 @ If bit-0 in r0 is set, OR it with r1 and update flags again
orreq r0, r0, #1 @ Else set bit-0 and do not update flags
It looks a bit complicated. The ORR instruction (OR Register) is simple enough; bitwise OR the contents of a register/immediate value. The NE and EQ conditions cause the instruction to only execute if the Z flag is set or cleared, respectively. The S switch causes the instruction to update the flags after the operation. (The TST instruction always updates flags; it is not optional.) If a condition is left off, it is assumed to be AL (always). Thus, ORR and ORRAL assemble to the same instruction.
And then, you have things like shift operands, which are also great for optimizations.
You can get more information here:
http://en.wikipedia.org/wiki/ARM_architecture